Johne, what is your problem? You're trying to argue about things no one ever claimed. No one said that the parity lower bound poses some fundamental limit to computing XOR with circuits other than those for which the theorem applies (i.e. AC^0 circuits). There are no hidden assumptions or veiled implications here. In particular we all know for example that it is possible to compute XOR with polynomial-sized NAND circuits of logarithmic depth, even with constant fan-in.

Shannon's quote is largely irrelevant too. There is no indication there that he even suspected that constant-depth AND-OR circuits need to have exponential size in order to compute Parity. Of course he might have guessed, since it is easy to conjecture this should be true after playing with the problem for a while, but so what?

You're missing entirely the point: proving lower bounds is exceedingly difficult, and we have to start somewhere, with the simplest models. This was essentially the first circuit lower bound, the techniques lead to many interesting ideas (including other fields such as learning theory), and although the result is plausible the proof is insightful and not at all trivial.

The fact that the result seems intuitive does not make it obvious; if you think it is, please provide a proof that parity is not in AC^0. Everyone knows that P is not equal to NP too for that matter, but nobody is anywhere near having a proof.

Your complaints in other threads about NAND gates make no sense either. This lower bound holds equally well for constant-depth circuits built up from NAND gates, as they're basically the same. Choosing to state the result with AND, OR, NOT it's just a matter of convenience. So this may be a real-world application in terms you like: constant depth circuits of NAND gates computing parity require exponential size. It does give a practical limitation, even if that's not the most important thing. It says that small XOR circuits for large number n of inputs must have either depth growing with n or gates other than NAND. Why aren't you satisfied with this?

Your claim that circuit depth is not an issue in the real world is also very misleading, since depth is directly related to time and the maximum frequency at which the clock can operate.

By the way, the CS community was well aware of the EE boolean circuit theory and built upon that, contrary to what you claim.

Johne, what is your problem? You're trying to argue about things no one ever claimed. No one said that the parity lower bound poses some fundamental limit to computing XOR with circuits other than those for which the theorem applies (i.e. AC^0 circuits). There are no hidden assumptions or veiled implications here. In particular we all know for example that it is possible to compute XOR with polynomial-sized NAND circuits of logarithmic depth, even with constant fan-in.

Shannon's quote is largely irrelevant too. There is no indication there that he even suspected that constant-depth AND-OR circuits need to have exponential size in order to compute Parity. Of course he might have guessed, since it is easy to conjecture this should be true after playing with the problem for a while, but so what?

You're missing entirely the point: proving lower bounds is exceedingly difficult, and we have to start somewhere, with the simplest models. This was essentially the first circuit lower bound, the techniques lead to many interesting ideas (including other fields such as learning theory), and although the result is plausible the proof is insightful and not at all trivial.

The fact that the result seems intuitive does not make it obvious; if you think it is, please provide a proof that parity is not in AC^0. Everyone knows that P is not equal to NP too for that matter, but nobody is anywhere near having a proof.

Your complaints in other threads about NAND gates make no sense either. This lower bound holds equally well for constant-depth circuits built up from NAND gates, as they're basically the same. Choosing to state the result with AND, OR, NOT is just a matter of convenience. So this may be a real-world application in terms you like: constant-depth circuits of NAND gates computing parity require exponential size. It does give a practical limitation, even if that's not the most important thing. It says that small XOR circuits for large number n of inputs must have either depth growing with n or gates other than NAND. Why aren't you satisfied with this?

Your claim that circuit depth is not an issue in the real world is also very misleading, since depth is directly related to time and the maximum frequency at which the clock can operate.

By the way, the CS community was well aware of the EE boolean circuit theory and built upon that, contrary to what you claim.