Does any body know any good reference for meaning of straight-line simulatability? I am currently deep into Universal Composability (UC) framework of Canetti but I can't find any good reference for meaning of straight-line simulatability. Any help is appreciated.
Here, "straight-line" is contrasted with "rewinding". A simulator is "straight-line" if it does not "rewind" the party it is doing the simulation for.
For instance, in a zero-knowledge protocol, the simulator usually rewinds the "verifier". In the "straight-line" sense, this rewinding does not happen.
I first saw the term "straight-line simulator" in Rafael Pass's paper (On Deniabililty in the Common Reference String and Random Oracle Models. (CRYPTO'03)) and M.Sc. thesis (Alternative Variants of Zero-Knowledge Proofs).
Edit: I found an earlier paper: Concurrent Zero-Knowledge: Reducing the Need for Timing Constraints by Cynthia Dwork and Amit Sahai, which dates back to 1998. For more pointers, see Alon Rosen's comment below.
There is no formal definition of what it means to be a straight line simulator. It is only a intuitive idea that can be used to describe things in an informal manner. I am highly skeptical about whether one can even define what it means to not rewind a machine. Indeed, rewinding a machine is itself an informal term! What we really mean by rewdinding a machine is that by we can explore many possible paths of execution of a machine from a given state. Formal arguments are then based on number of such executions we need to explore before we can obtain a trapdoor or some other information that we need to further continue our proof.