The definition of a $DLOGTIME$-uniform circuit family is based on a Turing machine that accepts the language $\langle t, a, b \rangle$, where gate $a$ is of type $t$ and has gate $b$ as a child, according to Barrington et. al's paper "On Uniformity Within $NC^1$" (1). However, this definition assumes that whether there is a wire or not between two gates is a binary choice. While this is true for $AND/OR$-based circuit classes like $AC^0$, other circuit classes like $CC^0$ and especially $TC^0$ assume that circuits can have an arbitrary constant or even $O(n)$ number of wires between two gates.
My questions are:
- Is there a standard way in the literature to extend the definition of dlogtime-uniformity with wire weights greater than 1?
- Is there a standard way to add this feature to logical characterizations of these families (e.g. $FO[bit]$)?