I have joined the hardware industry in the capacity of a formal verification engineer although my background is more of a theoretical logician.
I have this open question for the theoretical computer scientists, to identify the resources that get utilised in trying to convert an algorithm to some hardware implementation of the said algorithm. This is analogous to the flavour of identifying complexity resources to an algorithm. I want the resources that would be needed to manoeuvred to get the algorithmic implementation to an algorithm like say matrix multiplication ( which is used a lot in modern processors ).
In my limited experience it seems access to specific fundamental resources like an adder circuit or a multiplier circuit is where the bottlenecks get to, and the verilog implementation of these algorithms deal with timing accesses to these resources through staging them across distinguishable logical segments. Thus in particular at least few resources that I think of in the context of my question would be -> sub-routine oracles like the adder, multiplier circuits, clock, also perhaps physical size of the die to be designed.
I understand this might be more of an electronics engineering question, but I am trying to bridge two different disciplines and am hoping there would be some experts with this understanding having experienced both aspects. Also it seems the hardware industry is very closed as opposed to the community of theorists or even software engineers. I feel a lacunae in my understanding that I am not able to fully articulate. I am hoping a discussion will clarify the nuances. Resources that point to step by step conversion from a matrix/floating point multiplication pseudo-code to converting it to hardware implementation of it would be very welcome. Thanks.